1. Related Applications
Apparatus and Method for Data Copy Consistency in a Multi-Cache Data Processing Unit invented by Stephen J. Shaffer and Richard A. Warren, Ser. No. 06/698,364, filed on Feb. 5, 1985 and assigned to the assignee named herein.
Apparatus and Method for Improving System Bus Performance in a Data Processing System having a Plurality of Data Processing Units by Stephen J. Shaffer, Richard A. Warren, Thomas W. Eggers and William D. Strecker, Ser. No. 06/698,399, filed on Feb. 5, 1985 and assigned to the assignee named herein.
2. Field of the Invention
This invention relates generally to data processing systems and, more particularly, to data processing systems having a plurality of data processing units. In the data processing systems with a plurality of data processing units, the multiple copies of data signal groups stored in the cache memory units associated with each data processing unit provide increased opportunity for accessing a data signal group that is being manipulated simultaneously by at least one other data processing unit. In order to prevent inconsistent results from being obtained by the simultaneous manipulation, selected data signal groups are prevented from simultaneous manipulation by the data processing system.
3. Discussion of the Related Art
In data processing subsystems, a plurality of the system units such as data processing units and/or one or more peripheral subsystems, can attempt to access simultaneously a data signal group stored in the main memory unit. The simultaneous or overlapping access of the selected data signal groups by a plurality of data processing subsystems can result in inconsistent, ambiguous and erroneous data signal groups obtained that can impact the operation of the data processing system unless appropriate mechanisms are embedded in the data processing system.
One such mechanism is the use of a register position in the main memory that, once set, prevents further access of the main memory. This register position is set once access to the main memory is acquired, and further of the data signal group access is prohibited until the current access is complete and the register position signal is removed. This mechanism is sometimes described as an interlock mechanism.
However, a mechanism, that prevents access to the main memory unit for the duration of an operation by a data processing unit involving the selected data signal group, can impact the performance of the data processing system. In a data processing system having a plurality of data processing units, the continuing attempts of the data processing units to gain access to the main memory unit can cause non-productive bus traffic, comprising the performance of the data processing system.
A need has therefore been felt to prevent simultaneous use of selected data signal groups by a plurality of data processing units and to reduce system bus activity resulting from continuing attempts to access the prohibited data signal group.